David Wang

David Wang is a seasoned engineer with extensive experience in ASIC and FPGA design and verification. Currently serving as a Principal Design Engineer at Marvell Technology, David specializes in high-speed SERDES. Prior roles include Sr. FPGA Design Engineer at Ciena, where David focused on 5G network infrastructure, and Sr. FPGA/ASIC Design Engineer at Cornami, Inc., working on advanced hardware development. David's foundational expertise was established at Broadcom and Brocade as a Staff ASIC/FPGA Engineer, as well as at Foundry Networks as a Member of Technical Staff. Additional experience includes significant contributions at Lara Networks/Cypress Semiconductor, Nextware Corp., and HAL Computer Systems/Fujitsu. David holds a Master of Science in Electrical and Computer Engineering from Purdue University and a Bachelor of Science in Electronic Engineering from National Chiao Tung University.