Jack Zhang

Jack Zhang is an accomplished director in technical physical design at Marvell since May 2010, overseeing the development of advanced technology chip designs, specifically utilizing TSMC 3NM and 5NM processes. Prior experience includes serving as a Senior Staff Design Engineer and Project Lead at Plato Networks from December 2007 to May 2010, where responsibilities encompassed the entire physical design process for a 10 million instance project. Earlier in the career, Jack held the position of Principal Design Engineer at Cadence Design Systems between 2001 and 2007, focusing on chip tapeout and synthesis while developing eflow for design services. Education includes a Master’s degree in Electrical and Computer Engineering from Mississippi State University, where foundational work in BDD using C/C++ occurred as a student and research assistant from 1999 to 2001.