Peter Stanwicks is a Staff Engineer at Marvell Technology, specializing in ASIC Design Verification. They obtained a Bachelor's degree in Computer Systems Engineering and a Master's degree in Electrical and Computer Engineering from the University of Massachusetts Amherst, where they also worked as a Research Assistant and Teaching Assistant. At Marvell Semiconductor, they contributed to control/status register modeling and packet scheduling analysis. Prior to their current role, they gained valuable experience as a Design Verification Engineer, focusing on UVM SystemC implementations.
This person is not in any teams
This person is not in any offices