Raj Pednekar

Raj Pednekar is a Senior Staff Design Verification Engineer at Marvell Technology, with prior experience as a Sr. Logic Verification Engineer and Logic Verification Engineer at Analog Bits. Raj also worked as an Applications Engineer at Zuken and served as a Teaching Associate at San Jose State University. Raj holds a Master of Science (M.S.) in Electrical and Electronics Engineering from San Jose State University, obtained in 2017, and a Bachelor of Engineering (B.E.) in Electronics and Communications Engineering from K. J. Somaiya College of Engineering, completed in 2015.