Rajesh Pawar

Rajesh Pawar is an experienced SOC Verification Engineer at Marvell Semiconductor since July 2019. Prior to this role, Rajesh served as a Teaching Associate at San Jose State University, instructing Digital Logic Circuit Design and training students on FPGA design flow. Rajesh's internship at Synopsys Inc involved creating board-bring up utilities for the HAPS-80D Prototyping platform, while previous experience as a Design Verification Engineer at Imagination Technologies included SOC level verification and testbench environment development. Additionally, Rajesh worked as a Product Applications Engineer at Xilinx resolving customer issues related to FPGA, and started as a Junior Associate at Synechron focusing on test case execution and reporting. Rajesh holds a Master of Science in Electrical Engineering with a focus on VLSI from San Jose State University, a PG Diploma in VLSI Design from CDAC ACTS, Pune, and a Bachelor's Degree in Electronics and Telecommunication from Savitribai Phule Pune University.