Robert Bunce

Robert Bunce is a seasoned engineering professional with extensive experience in high-speed design and development. Currently serving as a Senior Principal Engineer at Marvell Technology since February 2019, Robert focuses on the architecture and logic design of a high-speed Network-on-Chip for multi-processor systems on a chip (SoC). Prior to this role, Robert was a Senior Staff Engineer at Qualcomm from September 2014, leading the development of custom Serdes Phy, PLL, and Physical Coding Sublayer (PCS) for server SoC applications. Robert's earlier career at IBM spanned over a decade, where responsibilities included logic design and management of a team focused on high-speed serializer/deserializer (Serdes) designs. Robert holds a Bachelor's degree in Electrical and Electronics Engineering from Worcester Polytechnic Institute and a Master's degree in Computer Engineering from National Technological University.