Cecilia Teo

Cecilia Teo is an experienced engineering manager with a robust background in integrated circuit design and project management. Since August 2020, Cecilia has served as a Senior Engineering Manager at MaxLinear. Prior to this role, Cecilia was with Intel Corporation from January 2014 to August 2020, initially as a Project Manager and later leading a SoC VLSI development team in the Connected Home Division. Between 2010 and 2013, Cecilia held the position of Design Project Leader at STMicroelectronics, focusing on secure microcontroller IC development. Earlier career experiences include roles as a Senior IC Design Engineer at Lantiq and Infineon Technologies, and a Design Engineer at Advanced Micro Devices, specializing in DSL network ICs and microprocessor implementation. Cecilia holds a Bachelor of Engineering in Electrical and Electronics Engineering from Nanyang Technological University Singapore.