Chaitanya Chigatapu

Chaitanya Chigatapu is a seasoned engineer specializing in analog design and RF applications, currently serving as a Senior Staff Engineer at MaxLinear since November 2022, focusing on RF ADCs and high-speed SerDes. Prior experience includes five years at Samsung India in the CMOS Image Sensor Group, where significant contributions were made to full chip analog top design and resolving silicon issues. Chaitanya also held roles as an Analog Design Engineer at Aura Semiconductor and as Design Engineer-II at Cadence Design Systems, working on high-speed ADCs and various analog circuits across multiple FINFET nodes. Chaitanya earned a Master's Degree in VLSI from the Indian Institute of Science and a Bachelor's Degree from SRKR Engineering College.