Michael Varuvel

Michael Varuvel possesses over two decades of experience in ASIC physical design, having held leadership roles in various prestigious companies. At MaxLinear, Michael served as an ASIC Physical Design Manager and Senior Principal ASIC PnR Engineer, overseeing the physical design processes for advanced low power and high-performance chips across multiple technology nodes down to 5nm. Prior experience includes a tenure as Physical Design Technical Lead at KPIT Cummins Infosystems Limited, where Michael managed the complete physical design activities for multi-million gate designs in multiple technology nodes. Additionally, Michael worked at Arm as a Sr. Design Engineer, contributing to key core implementations and collaborating on tool evaluations. The career began at Spike Technologies with a focus on standard cell layout design and library generation.