Sachin Mankal

Sachin Mankal is a Principal SoC Design Engineer at MaxLinear, leveraging over 15 years of extensive hands-on experience in ASIC IP/SOC RTL design. They have excelled in the complete SOC/IP development cycle, from architecture definition to post-silicon support, and possess expertise in a variety of protocols including PCIe 6 and IEEE 802.11 WLAN MAC. Sachin's innovative contributions include co-authoring a patent for low latency wireless transfer technology. Previously, they held significant roles at Intel, Qualcomm, and Marvell, showcasing their collaborative skills across global teams. They earned a Bachelor of Engineering in Electronics & Communication from Ramaiah Institute of Technology.