Ramesh mynala

Ramesh Mynala is a Senior Design Verification Engineer at MediaTek in Bangalore, where they focus on verifying Ethernet protocols, DMA, and ARM Cortex M4 at the SoC level. Previously, Ramesh worked as an ASIC Design Verification Engineer at Yoctozant Technologies from 2021 to 2025 and completed a trainee position at Sandeepani School of VLSI Design in 2020. Ramesh holds expertise in various protocols such as UART, SPI, APB, AHB, AXI, and I2C, and possesses skills in System Verilog Assertions, testbench components, and gate-level simulations, along with proficiency in Python and Perl scripting. Ramesh's educational background includes an SSC from ZPPSS and an Intermediate degree in M.P.C from Shivani Jr College, Warangal.