Anand Kane has a diverse background in ASIC engineering, with experience spanning several prominent technology companies. Anand Kane began in 2013 as a Co-op Engineer at AMD, contributing to performance verification of x86 CPU core models. From 2014 to 2016, Anand Kane served as an ASIC Engineer at Ericsson, focusing on RTL design for network processors. Anand Kane then transitioned to Google, where from May 2016 to May 2025, contributions included architecture and RTL design for machine learning inference accelerators such as the Google Tensor TPU and Edge TPU. Since May 2025, Anand Kane has been an ASIC Design Engineer at Meta, working on AR/VR machine learning silicon. Anand Kane holds a Master of Science degree from North Carolina State University, obtained in 2014.
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