Richard Phelps

Richard Phelps possesses extensive experience in ASIC design and SoC architecture, currently serving as a Principal ASIC Design Engineer at Infineon Technologies since January 2000. Expertise includes high-speed bus designs, interface implementation, and various aspects of design verification such as VHDL and Verilog coding, synthesis, timing, and power analysis, along with safety analysis in compliance with ISO26262. Previous roles as a Design Engineer at companies such as PixelFusion and STMicroelectronics focused on similar areas of SoC design, including external memory interface implementation. Richard commenced a career at GEC Plessey Semiconductors, contributing to VHDL coding and IC layout. Richard holds a Bachelor of Engineering in Electrical and Electronics Engineering and a Higher National Diploma in the same field from the University of South Wales.