Damien JEAN

Senior Asic Design Engineer at Scalinx

Damien JEAN has over 15 years of experience in the field of hardware and ASIC design. Damien is currently working at SCALINX as a Senior ASIC Design Engineer since December 2019. Prior to that, they worked at Sequans Communications from November 2015 to March 2021, initially as an Asic Design Engineer and then as a Senior Asic Design Engineer.

Damien also has experience working at Imagination Technologies as a Hardware Design Engineer from November 2012 to November 2015, where they gained skills in system level design and ASIC/SoC design flow. Before that, they worked at Alcatel-Lucent as an FPGA Design Engineer from January 2011 to October 2012.

In addition to their work experience, Damien had placements at various companies during their studies. Damien worked as an FPGA Design Engineer at Elsys Design from September 2008 to December 2010, where they were involved in FPGA/VHDL design on Xilinx Virtex4FX60 and Virtex5LX110T. Damien also had a placement as a Network Administrator at France Telecom R&D from December 2008 to July 2009 and as an FPGA Designer at France Telecom R&D from April 2007 to November 2007.

Damien started their career with a placement at HEIG-VD as an FPGA and Hardware intern in the REDS Institute in 2006. Prior to that, they had a placement at homerider Systems as a Hardware & Software intern in 2004.

Overall, Damien JEAN has a strong background in hardware and ASIC design, with experience at various companies in different roles.

Damien Jean began their education by obtaining a high school diploma in Analog & Digital electronics from Lycée Galilée Technical High School in Vienne, France, from 2000 to 2002. Damien then pursued a two-year university technical degree (DUT GEII) at Université Joseph Fourier (Grenoble I) from 2002 to 2004, specializing in Embedded systems, Analog & Digital electronics, and Control Automation. Damien then went on to earn a Master of Engineering (Diplôme d'ingénieur) in Microelectronics, Embedded systems, and Instrumentation (3I) from Polytech' Grenoble at Université Joseph Fourier (Grenoble I) from 2004 to 2007.

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Timeline

  • Senior Asic Design Engineer

    March, 2021 - present