Juyoung Kim

Juyoung Kim is a seasoned digital design engineer with extensive experience in developing advanced technologies for prominent companies in the industry. Currently at Meta since June 2025, Juyoung focuses on the digital design of texture buffer management blocks for GPUs utilized in smart glasses. Prior to Meta, Juyoung served as a Principal Engineer at SK hynix from September 2022 to May 2025, where contributions included the development of digital logic for high-speed interface IP using TSMC's 7nm process, emphasizing optimized power, performance, and area (PPA). As a Senior Staff Engineer at Samsung Electronics from April 2012 to May 2022, Juyoung contributed to multiple IP developments for mass production, including PCIe Gen4 and USB 3.1 Type-C. Earlier experience includes work as a Senior Engineer at MTEKVISION, where Juyoung designed RTL for DSP sub-blocks in camera image processors. Juyoung holds a Master's degree in Electronic Communication Engineering and a Bachelor's degree in Electronic Computer Communications from Hanyang University.