Sahithi P. is a skilled engineer with extensive experience in silicon design and ASIC implementation. Currently serving as an ASIC Implementation Engineer at Meta since November 2025, Sahithi has previously held positions at AMD from November 2021 to January 2025, progressing from MTS Silicon Design Engineer to Senior Silicon Design Engineer. Prior to that, Sahithi worked as a Senior Design Engineer 1 at Xilinx for a brief period in November 2021 and as a Senior Synthesis and STA Engineer at MediaTek from June 2018 to November 2021. Sahithi holds a Master of Engineering in Microelectronics from the Birla Institute of Technology and Science, Pilani, completed in 2018.
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