Weikang Cheng is a seasoned engineer with extensive experience in ASIC design, currently serving as a Sr. Staff ASIC Design Engineer at Microchip Technology Inc. since August 2015, where responsibilities include RTL design, synthesis, and laboratory testing for GPHY applications. Weikang also contributes to GPHY digital design and verification as a Senior Design Engineer. Previously, Weikang has been with Micrel since February 2010, holding positions as Sr. Staff Design Engineer and Engineer, focusing on design, verification, IP documentation, synthesis, prime time analysis, analog modeling, design validation testing, and debugging. Academically, Weikang Cheng earned a Master of Science in Electric Engineering and a Master of Science in Computer Engineering from Syracuse University between 1987 and 1990.
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