Yashwanth Dandu

Yashwanth Dandu is a Senior Engineer in Layout Design at Mirafra Technologies, specializing in projects for Qualcomm, focused on TSMC's 3nm and 2nm nodes since February 2025. Prior experience includes an Engineer role in Layout Design at ACL Digital, where contributions were made for Intel's 18A, UMC's 22nm, and DBHitek 180 Compilers from March 2023 to February 2025. Earlier, Yashwanth worked at Insemi Technology Services Pvt. Ltd., developing SRAM for 10nm and 14nm processes and contributing to Analog Layout Blocks from March 2022 to February 2023. An internship at the Indian Institute of Remote Sensing (ISRO) in 2021 provided exposure to Remote Sensing, GIS, and Geocomputation. Yashwanth holds a Bachelor's degree in Electronics and Communications Engineering from Jawaharlal Nehru Technological University Anantapur, completed in June 2022.