JAYDEEP BHATT

Jaydeep Bhatt began their career in 2013 as a Project Lead and Sr. Engineer at Mobiveil Inc. In this role, they worked on NAND flash characterization process on TLC and MLC devices with MATLAB and FPGA based system, LDPC RTL modification and feature updates, handling existing customer release/updates and new queries or feature requirements, and leading the current team. JAYDEEP also served as an Engineer and a GET at Mobiveil Inc., where they worked on SPI/I2C IP board level validation (Altera FPGA-cyclone V), a turn key project for NVDIMM controller starting from FPGA device feasibility study to FPGA implementation and validation, and RTL Development of a few system components, glue logic and basic firmware based sanity tests of the system. In 2021, Jaydeep Bhatt was promoted to Project Manager - Design at Mobiveil Inc.

Jaydeep Bhatt attended GTU PG SCHOOL from 2011 to 2013 and earned a M.E. EC (VLSI & EMBEDDED SYSTEM DESIGN) degree in the field of VLSI Frontend & Backend.