Jialue Wang is a highly skilled Principal Design Engineer at Monolithic Power Systems, Inc. since August 2025, with extensive experience in analog IC and power management design. Prior to this role, Jialue served as a Senior Principal Analog Design Engineer at Nexperia from 2020 to August 2025, where responsibilities included the development of power management IC products and translation of product functional requests into circuit specifications. Previous positions include Principal Analog IC Design Engineer at Nexperia, Analog IC Design Engineer at Nowi, and various roles at imec, culminating in a Doctor of Engineering degree from Eindhoven University of Technology. Jialue's educational background also includes a Master of Science degree from Delft University of Technology, emphasizing expertise in electrical and electronics engineering.
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