Mesbah Karim

Mesbah Karim has been working in the hardware design engineering field since 2002. Mesbah began their career at Intel Corporation, where they held three positions as Staff Design Engineer, Staff Design Engineer/Senior Design Engineer, and Staff Design Engineer. During their time at Intel, they were responsible for bus control logics, cache and register control logics, and clock, reset, Iscan and Scanout logics for memory controller cluster. Mesbah also developed a script and methodology to analyze retiming results from synthesis. In 2016, they moved to a Stealth Mode Startup Company as a Senior Staff FPGA Design Engineer. From 2017 to 2019, they worked at Sensity Systems, Inc., a Verizon company, as a Senior Embedded/FPGA Design Engineer. During this period, they also worked at StreamtvNetworks as a Principal RTL/Logic Design Engineer. In 2019, they joined EdgeCompute Inc. as a Senior RTL/Logic Design Engineer, where they defined micro-architecture and RTL implementation of memory sub system, designed and implemented memory array architecture, implemented pipeline flow for read-write access, and wrote unit level tests. Mesbah is currently employed at MoSys, Inc. as a Staff Hardware Design Engineer.

Mesbah Karim has obtained a Master of Science (MS) degree in Electrical and Electronics Engineering from The University of Texas at Arlington, and a Master of Science (MS) degree in Computer Engineering from Bangladesh University of Engineering and Technology. Additionally, Mesbah Karim has obtained six Coursera Course Certificates between September and December of 2016, including Introduction to Programming with MATLAB, Using Databases with Python, Programming for Everybody (Getting Started with Python), Python Data Structures, and Using Python to Access Web Data.