Turan Cakiraga began their professional career in 1991 as an Engineering Project Leader and Lead ASIC Design Engineer for EMC Corporation. In 1992, they moved to Cadence Design Systems Inc. as a Senior Customer Support Application Engineer. turan then joined MENTOR Graphics Inc. in 1993 as a Field Application Engineer. In 1995, Cakiraga began working for Fujitsu Nexion Inc. as a Hardware Verification Engineer. In 2000, they joined Juniper Networks Inc. in the same role. In 2007, they became a Design Verification Consultant for Qualcomm. turan then worked as a Verification Engineer Consultant for Professional Verification Services from 2002-2011. In 2011, Cakiraga began working for Netronome as a Senior Design Verification Engineer. In this role, they built multiple SystemVerilog/UVM based test bench environments to verify subsystems for a network flow processor. turan also developed a variety of verification components, wrote verification plans, and more.
Turan Cakiraga received a Bachelor of Science in Electrical Engineering from Northeastern University and a Master of Science in Electrical Engineering from Tufts University.
September, 2011 - present
Senior Design Verification Engineer at Nexperia
Senior Design Verification Engineer at ACL Digital
Senior Design Verification Engineer at Marvell Technology
Senior Design Verification Engineer at Axelera AI
Senior Design Verification Engineer at U Blox Holding AG
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