DP

Draginja Pesic

Verification Engineer at NextSilicon

Draginja Pesic is a seasoned verification engineer with extensive experience in the field. Currently employed at Vtool - Smart Verification since January 2020, Draginja previously held the same title at HDL Design House from September 2013 to January 2020. Earlier in the career, Draginja worked as a C developer at Seavus from February 2008 to March 2010. Draginja completed studies at the University of Belgrade, Faculty of Electrical Engineering, from 1993 to 2000.

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