Ritika Kohli is a Senior ASIC Design Engineer at NVIDIA, where they support physical design and timing closure efforts for Tegra SOCs. Prior to this role, they worked as a Senior Design Engineer at Analog Devices, focusing on timing closure activities for digital modules, and as a Component Design Engineer at Intel Corporation, mainly dealing with signoff timing closure. Ritika also held positions at Cadence Design Systems and STMicroelectronics, contributing to product validation and automotive product synthesis, respectively. They earned a Master of Technology in Microelectronics from the Birla Institute of Technology and Science, Pilani, and a Bachelor's degree from JSS Academy of Technical Education, Noida.
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