Jagdish Agrawal

Jagdish Agrawal brings over 23 years of experience in digital design while working in various companies including Texas Instruments, Maxim Integrated, Motorola, and Infineon Semiconductors.

Jagdish has executed and managed very high-speed complex ASIC/IC projects in deep submicron technology including implementations of complex digital signal processing-based algorithms, high-performance DDS-NCOs, digital up convertor blocks, FIR filters, memory controllers, etc. He has successfully executed complex RF DAC Gigasample-per-second designs used for the cellular base stations, Cable modem, OFMD plus SCQAM modulator DUC.

Additionally, he has successfully executed various projects in the wireless communication such as 160 channel Downstream Cable QAM Modulator, Integrated OFDM and SCQAM Modulator for Downstream Cable, Fully Integrated 3.2GSPS RF ADC DPD Receiver, 6/12GSPS Small cell transceivers, Transceivers for SISO/MIMO application, IEEE1394 PHY and Link layer and DS3/E3 ASICs. Jagdish obtained his B.E. (Electronics and Communications) degree from MNREC (Allahabad) in ’96.