Regis Desrosiers

Regis Desrosiers is a skilled hardware engineer with extensive experience in electronic circuit design and FPGA design in VHDL. Currently, Regis works at Orthogone Technologies Inc. since April 2021, having previously held similar roles at Semtech from April 2017 to April 2021 and Averna from May 2008 to April 2017. At Averna, Regis contributed to projects such as a realtime H264 HD video encoder and a DOCSIS protocol analyzer. Earlier experience includes digital design work at SRTelecom from January 1999 to April 2008, involving the design of various electronic components. Regis holds a Bachelor of Engineering in Electrical, Electronics and Communications Engineering from Université de Sherbrooke and a DEC in Sciences from Collège de Maisonneuve.