Erasmo Chiappetta Filho

Erasmo Chiappetta Filho has a diverse work experience in the field of electronic design and engineering. Erasmo currently holds the position of Chip Lead Engineer at Pharrowtech since June 2022. Prior to this, they worked at AnSem from 2016 to 2022, where they served as a Project Leader ASIC Design from July 2019 to June 2022 and as a Senior Analog/Mixed-Signal Design Engineer from June 2016 to June 2019.

Before joining AnSem, Erasmo worked as an Analog IC Design Engineer at the Eldorado Research Institute from September 2009 to June 2016. Erasmo also gained experience as an Analog and Mixed Signal IC Designer during their time at the IC-Brasil Training Program from March 2009 to September 2009. Additionally, they worked as a Junior Researcher at the Nangate UFRGS Research Lab from August 2007 to January 2009, where they focused on automation of standard cell library characterization, generation of Liberty files, and research on delay and power consumption estimation for logic cells.

Erasmo's early career involved working as a Junior Researcher at the Laboratório de Eletrônica de Potência (LEPUC) at PUCRS from May 2005 to December 2005.

Erasmo Chiappetta Filho obtained a Master's Degree in Microelectronics from the Universidade Estadual de Campinas, which they attended from 2012 to 2015. Prior to that, in 2009, they completed a training program in Analog and Mixed Signal IC Design at the IC-Brasil Training Program. Erasmo obtained a B.S. in Electrical Engineering from the Federal University of Rio Grande do Sul, where they studied from 2005 to 2009. Before entering university, Erasmo attended the Pontifícia Universidade Católica do Rio Grande do Sul from 2001 to 2005, where they pursued a degree in Engenharia Elétrica. Further details about their education prior to university are not available.