Sagar Jagtap

Sagar Jagtap is an experienced Digital ASIC Engineer with a significant background in chip design and verification. Sagar worked at Presto Engineering as a Digital ASIC Engineer, where they were responsible for coding, memory BIST implementation, and defining synthesis timing constraints. Prior to that, Sagar worked at Oticon A/S as a Digital ASIC Designer, handling tasks such as I2S design, chip-level timing constraints, and formal equivalence checks. Sagar also evaluated digital blocks in the lab. Sagar was a Consultant at SyoSil, where they worked on Agile development, UPF implementation, and Sprint Planning. At Ericsson AB, Sagar contributed to RTL2GDSII ASIC design, performing tasks like static timing analysis and chip topography aware synthesis. Sagar also worked as a Master Student at both Ericsson AB and IMEC, where they focused on timing constraint quality check, automation of tool flows, and variability in CMOS technology.

Sagar Jagtap completed an Introduction to Sustainable Electric Power Systems course at KTH Royal Institute of Technology in 2022. Prior to that, they obtained a Master of Science degree in System-on-Chip from The Faculty of Engineering at Lund University, which they completed from 2005 to 2007. Before pursuing their master's, Sagar earned a Bachelor of Engineering degree in Electronics & Telecommunication from Savitribai Phule Pune University, where they studied from 2000 to 2004.