Synopsys
Vinodhini Radhakrishnan is an experienced ASIC Digital Design Senior Engineer at Synopsys Inc since June 2025, previously serving as a Validation Design Engineer on contract at NXP Semiconductors from May 2024 to May 2025, where expertise included developing tests for low-speed interface validation and characterizing protocols such as SPI, I2C, QSPI, and OSPI. Prior to that, Vinodhini worked as a Senior Project Engineer at Soliton Technologies from April 2021 to May 2025, focusing on automation frameworks for validation infrastructure and real-time monitoring applications. Vinodhini's earlier roles include Project Engineer, Embedded Software Engineer Trainee, and innovation engineer trainee. Education was completed at Kumaraguru College of Technology with a Bachelor of Engineering in Mechatronics, Robotics, and Automation Engineering in 2021.
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