Elad Chermon

Elad Chermon has over 20 years of experience in the field of semiconductor design and verification. Elad began their career as a Board Designer at RADVISION in 2000. From 2002 to 2007, Elad worked at Freescale Semiconductor, where they served as an RTL Designer and Verification Engineer. During this time, they focused on new design implementations for passing signals between clock domains and was involved in enhancing On Chip Emulation (EONCE) and JTAG technologies.

In 2007, Elad joined Xelerated - Marvell, where they worked as an ASIC Design and Verification Engineer. In this role, they were responsible for verification planning, testbench implementation, monitoring, and coverage generation. Elad also played a key role in RTL design, particularly in microarchitecture planning and implementation for IP packet fragmentation and status formatting blocks.

Most recently, Elad has been working at Ramon Chips Ltd. as a Senior Verification Engineer since 2015. Their responsibilities include planning and executing block-level and system-level verifications for a multi-DSP chip memory access sub-system. Elad has also developed and coded a SystemVerilog UVM-based testbench, complete with agents, scoreboards, and coverage.

Overall, Elad Chermon's work experience showcases their expertise in verification, RTL design, and semiconductor technologies.

Elad Chermon attended Tel Aviv University from 1997 to 2001, where they obtained a Bachelor's Degree in Electrical and Electronics Engineering.