Meghana Desai

Meghana Desai has extensive work experience in the engineering field. Meghana began their career in 2000 as an Intern at ISRO-Space Application Center, where they implemented FFT algorithm on DSP processor ADSP-21020 and FPGA. In 2001, they took on the role of VLSI Lab Coordinator and Teaching Assistant at DA-IICT. In 2006, they became a Trainee at Cadence Design Systems, where they validated ECSM support for standard cell library parser for synthesis tool RC 6.2 and validated state-table support in RTL Compiler. From 2011 to 2015, they worked as a Digital/RTL Logic Designer at Greenvity Communications, where they performed implementation and verification of Packet Detector, Shaping, DC Offset estimate and correction, Sampling offset estimation, FIR Filters, offset QPSK, Packet Parser and Rx State Machine. From 2015 to 2020, they served as an Application Engineer Sr II and CAE Sr I at Synopsys Inc. During this time, they also took on the role of Staff Application Engineer at Ansys. Currently, they are a Sr Staff Application Engineer at Real Intent.

Meghana Desai completed their Master of Technology (M.Tech.) in Information & Communication Techonology from DAIICT Gandhinagar Gujarat in 2007. Prior to that, they completed their Master of Science (M.Sc.) in Electronics from School of Sciences, Gujarat University in 2001. Meghana also completed their Bachelor of Science (B.Sc.) in Electronics & Physics from St Xavier's College, Ahmedabad Gujarat in 1999.