Ioannis Papadogiannis

Ioannis Papadogiannis currently serves as Digital IC Lead at Renesas Electronics since May 2024, following a similar role at Adveos from January 2022 to May 2024. Prior experience includes positions as ASIC Engineer at Apple from November 2019 to December 2021 and Digital Design Engineer at Intel Corporation from January 2016 to October 2019, specializing in high-speed RTL design. Earlier roles involved low power RTL design at Dialog Semiconductor and software development at Intracom Telecom and Danaos Management Consultants S.A. Ioannis began a career in hardware engineering, focusing on RTL design for FPGAs at BCL Electromagnetics Ltd. Ioannis holds both a Master of Science and a Bachelor of Science in Electrical and Computer Engineering from the University of Patras.