Ze'Ev Gal

Ze'ev Gal is an experienced engineer specializing in FPGA verification with a background in hardware validation, machine learning, and electronics engineering. Currently serving as an FPGA verification engineer at Ribbon Communications since November 2021, Ze'ev designs verification environments for advanced FPGA modules. Previous roles include machine learning research for drug discovery at Ben-Gurion University of the Negev, verification engineering at Intel Corporation, and validation engineering at Vertech. Ze'ev's extensive experience also includes work as an electronics engineer at NDS, design engineering at NXP (formerly Freescale Semiconductor), and as an electronics engineer officer in the IDF. Ze'ev holds a Bachelor of Applied Science in Electrical, Electronics and Communications Engineering from Lev Academic Center and completed a course in deep learning at Primrose.