Magesh Subramni

Magesh Subramni is a Senior Manager of IC Design at Saankhya Labs. Magesh has over fifteen years of experience in the semiconductor industry. Magesh started their career as a Member of Technical Staff at Sage Design Systems India Pvt Ltd where they were responsible for verifying the I2C slave core and SRAM controller. Magesh then moved to Genesis Microchip where they were a Senior Member of Technical Staff. Their primary responsibility was to support product development which included RTL design, sub-system eVC development, few core blocks ASIC synthesis, formal verification at module and full-chip level, and sub-system and peripheral timing closure. Magesh was also responsible for test program development of FLI2300 and its derivative products. In their current role as Senior Manager of IC Design at Saankhya Labs, Magesh is responsible for the design, development and integration of digital, mixed-signal and analog integrated circuits.

Magesh Subramni has a B.E in Electrical and Electronics from the Institute of Road and Transport Technology, Erode and a Diploma in Electrical and Electronics Engineering from TPEVR Polytechnic.

Magesh Subramni reports to Anindya Saha, CTO. They work with Hemant Mallapur - Founder & EVP, Engineering, Paresh Krishnakant Joshi - Director, SoC Development, and Sunil HR - VP, Technology & Solutions.