KJ Lee is a Principal Engineer at Samsung Electronics, specializing in advanced package development and reliability within the Advanced Package Development Team. With over 15 years of experience in electronic packaging reliability, KJ has expertise in solder joint reliability, warpage data analysis, and SMT technologies. KJ has held notable positions at Intel, where they led cross-functional teams and managed system-level assessments, and conducted research at Shanghai Jiaotong University. KJ holds both a Bachelor’s and a Master’s degree in Mechanical Engineering from the Georgia Institute of Technology.
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