Kevin Heldt

Kevin Heldt is a Staff FPGA Engineer at SEAKR Engineering since April 2008, specializing in FPGA architecture, Verilog and VHDL coding, and comprehensive design processes. Expertise includes large-scale Flash memory controller design, high-speed serial and DDR3 memory systems, and SEU mitigation strategies. Heldt has collaborated with the Xilinx Radiation Test Consortium, leading experiments and publishing findings, and has extensive experience in test system design and board design with signal integrity analysis. Prior to SEAKR, Heldt worked as a Senior Electrical Engineer at Raytheon, focusing on FPGA design and dual embedded microprocessor systems. Heldt holds a BS in Electrical Engineering from California Polytechnic State University-San Luis Obispo.