Bala Murali Krishna Baisani

Bala Murali Krishna Baisani is an experienced design verification engineer currently working at UST since June 2021, where roles have included Engineer - 1, Associate Engineer - A2, and Associate Engineer - A1. Prior to UST, Baisani completed a training program in RTL design and verification at Maven Silicon from November 2020 to June 2021. Earlier experience includes a position as a Biomedical Technician apprentice at CARE Hospitals in 2016. Baisani holds a Bachelor of Technology degree in Electronics and Communication Engineering from Sri Venkateswara University and a Special Diploma in Electronics (Bio-medical) from the Government Institute of Electronics. Education also includes completion of SSC at Sri Sarawati Vidhya Mandir.