Samriddhi Chaki

Samriddhi Chaki is an Associate Design Verification Engineer at UST since January 2022, with prior experience as an RTL and Verification Trainee at Maven Silicon from February 2021 to January 2022. Previously, Samriddhi completed a Graduate Internship at Intel Corporation from July 2019 to June 2020, focusing on Pre-Si IP Validation of PMC-IP using SystemVerilog within an OVM-based verification environment, and contributed to project work that involved creating scalable validation collateral and utilizing automated tools for IP validation. Samriddhi holds a Master of Technology in VLSI from Vellore Institute of Technology (2018-2020) and a Bachelor of Technology in Electrical and Electronics Engineering from Sir M Visvesvaraya Institute of Technology (2013-2017).