Sijo Mathew

Sijo Mathew is an experienced FPGA Design Engineer currently working at SeviTech Systems Pvt. Ltd. since December 2019, focusing on 5G PDSCH utilizing C HLS, Verilog, and Digital Signal Processing. Prior experience includes a role at Avantel Limited where Sijo developed RTL Verilog code for satellite-based FPGA modems, and as a VLSI Design Engineer at Ronicslabz, where Sijo optimized designs for timing, area, and power efficiency. Earlier career at Green Info Solutions involved embedded engineering with responsibilities such as test bench development and verification using simulation tools like Xilinx and Modelsim. Sijo holds a Master’s Degree in VLSI Design from Hindustan Institute of Technology and an Engineer’s Degree in Electronics and Communications Engineering from Cochin University of Science and Technology. Skills include RTL Verilog, FPGA design, and digital signal processing.