Srihari V S

Srihari V S is a Design Verification Engineer at UST since June 2021, with prior experience as an Engineer - 1 and Associate Engineer A2. Before UST, Srihari V S worked as an RTL Design and Verification Trainee at Maven Silicon from September 2020 to May 2021. An early experience includes an internship at Vitvaraa Electronics Private Limited in the Internet of Things sector during June 2019 to July 2019. Srihari V S holds a Bachelor of Engineering degree in Electronic and Communications Engineering from the University BDT College of Engineering, attained in 2020, and completed PUC at Alva's College of Education from 2014 to 2016.