Raghav Chawla

Raghav Chawla is a Staff Engineer in CPU Physical Design at SiFive, where responsibilities include leading the physical design convergence for high-performance P Series Cores and driving RTL analysis for performance enhancements. Prior roles include Senior Engineer at SiFive, focusing on RISC-V CPU cores, and a position at Google within the CPU Core Physical Design Team, contributing to the PPA convergence of Google Tensor SOCs and the floating-point unit targeting 3 GHz performance. Experience at Intel Corporation involved optimizing PPA for graphics hardware, while an internship at STMicroelectronics focused on developing a feedback algorithm for timing mismatch issues in DAC structures. Raghav Chawla holds a B.Tech in Electronics and Communications Engineering from the Indian Institute of Technology, Roorkee.