Akhila Gangavarapu

Akhila Gangavarapu is a Senior CAD Engineer at Silicon Labs since November 2018, having progressed through several roles including CAD Engineer II and CAD Engineer. Prior experience includes working as a Device Engineer at GLOBALFOUNDRIES from March 2016 to November 2018, specializing in library characterization, synthesis, and place-and-route (P&R) operations, notably on 7nm standard cells for performance optimization. Earlier, Akhila contributed as an RF Optimization Engineer for the Samsung Clearwire project at Metapro Solutions, focusing on analyzing voice calls and LTE connection issues. Initial roles included a Network Engineer position and academic support at the University of Missouri-Kansas City. Akhila holds a Master's degree in Electrical and Electronics Engineering from the University of Missouri-Kansas City and a Bachelor's degree in Electrical, Electronics, and Communications Engineering from Jawaharlal Nehru Technological University.