Kaustubh Apte

Kaustubh Apte has a long history of work experience in the engineering field. Kaustubh began their career in 2012 as a Summer Intern at Siemens India P Ltd., where they worked with the project team to understand the deployment of SCADA networks in the field and visited substations. In 2013, they became an Interim Engineering Intern at Qualcomm, where they developed a "Hold Violation Analyzer" script using Perl and Tcl. In 2014, they joined Qualcomm as an Engineer, Associate and was a part of the Physical Design team. During their time there, they implemented hard-macros and tiles from netlist to gds on the latest technologies and process nodes. Theirrole included partitioning, floorplanning, constraints correlation checks, UPF-based PnR, raw-clock and clock-tree analysis, power and signal integrity, logic and low-power equivalence check, timing closure/ECO generation, and physical verification. In 2017, they joined Intel Corporation as a SoC Design Engineer. Most recently, in 2022, they began working at SiMa.ai as an ASIC Physical Design Engineer.

Kaustubh Apte attended the National Institute of Technology Karnataka from 2010 to 2014, where they earned a Bachelor of Technology (B.Tech.) in Electrical and Electronics Engineering.