Viral Pandya

Viral Pandya has been in the engineering industry since 2003. Viral started as the Director of Engineering at RMI Corporation in 2003 and moved on to become the Director of Engineering at NetLogic Microsystems in 2009. In 2012, they joined Broadcom Corporation and Broadcom Limited as the Senior Director of Engineering. Viral worked on ARM V8.2 and was responsible for MultiThreaded/MultiCore datacenter silicon development with 32 CPU cores, Mesh Interconnect, 8 DDR4 channels, 56 PCIe-Gen3 lanes, SATA, USB, and high-speed inter-chip interface (ICI). In 2016, they moved to Marvell Semiconductor & Cavium as the Senior Director of Engineering and worked on ARM V8.4 CPU core, MultiThreaded/MultiCore datacenter silicon development with 60 CPU cores, Mesh Interconnect, 8 DDR4 channels, 64 PCIe-Gen4 lanes, SATA, USB, and high-speed inter-chip interface (ICI). In 2021, they joined SiMa.ai as the Senior Director of Engineering and is working on delivering the industry's first software-centric purpose-built MLSoC platform.

Viral Pandya holds a Master of Science degree in Electrical and Computer Engineering from Arizona State University.