Sivaganesh Jyothula

SivaGanesh Jyothula is an experienced AMS Layout Design Engineer currently working at SmartSoC Solutions Pvt Ltd since April 2024, focusing on TSMC 7nm technologies and conducting various physical verification checks. Prior to this, SivaGanesh worked at SignOff Semiconductors from July 2021 to March 2024, engaging with multiple process nodes including TSMC 7nm, 16nm, 28nm, and TSL 180nm, while also performing similar physical verification tasks. SivaGanesh began professional career as a Process Associate at Wipro from December 2019 to April 2021, handling non-voice processes. SivaGanesh holds a B.Tech degree in Electronics and Communications Engineering from Adarsh College of Engineering, completed in April 2018.