Sri Chaitanya Veeraboina

Physical Design Engineer at soctronics

Sri Chaitanya Veeraboina is a seasoned Physical Design Engineer with experience at AMD as a contractor since July 2021 and at Soctronics since January 2020. Prior to these roles, Sri Chaitanya served as a Trainee at VEDA IIT from May 2019 to January 2020. Academically, Sri Chaitanya holds a Bachelor of Engineering degree in Electrical, Electronics and Communications Engineering from Matrusri Engineering College, achieved in 2019.

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