Pappu Burnwal is a Senior Design Engineer at STMicroelectronics, with a strong foundation in layout design and validation. They have hands-on expertise in library cell layouts across various technology nodes, including 5nm to 90nm, and are skilled in addressing design challenges such as latch-up problems and signal integrity. Previously, Pappu worked as a SoC Design Engineer at Intel Corporation and completed advanced degrees in Instrumentation and Electronic Engineering from the National Institute of Technology Kurukshetra and Asansol Engineering College, respectively.
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