Andranik H.

Andranik H. is an experienced ASIC Physical Design Lead currently working at a Stealth Mode AI Startup since December 2023, focusing on ASIC RTL2GDS physical design and DFT. Previously, Andranik H. served as ASIC Physical Design Leader at Cisco from February 2014 to October 2023, where responsibilities included floorplanning, physical aware synthesis, custom placement, clock planning, signal routing, and ensuring timing and physical closure. Prior to Cisco, Andranik H. worked as a Senior R&D Engineer at Synopsys from January 2008 to February 2014, specializing in the physical design of analogue and mixed-signal blocks as well as chip planning.