Nazneen Jeewakhan

Nazneen Jeewakhan is a highly experienced Process Development Engineer specializing in lithography, currently employed at SVTC since 2007. In this role, Nazneen is responsible for lithography process development for various technologies, including CMOS, Biochips, and MEMS, employing a range of tools such as 193nm, 248nm, and 365nm. Prior to SVTC, Nazneen worked at Cypress Semiconductor from March 2001 to March 2007, where responsibilities included the development of 65nm gate layer lithography processes and the successful transfer of back end layers for the 90nm technology node from R&D to production. Nazneen holds a Master's degree in Chemical Engineering from the University of Southern California, obtained between 1999 and 2001.