SVTC
Nazneen Jeewakhan is a highly experienced Process Development Engineer specializing in lithography, currently employed at SVTC since 2007. In this role, Nazneen is responsible for lithography process development for various technologies, including CMOS, Biochips, and MEMS, employing a range of tools such as 193nm, 248nm, and 365nm. Prior to SVTC, Nazneen worked at Cypress Semiconductor from March 2001 to March 2007, where responsibilities included the development of 65nm gate layer lithography processes and the successful transfer of back end layers for the 90nm technology node from R&D to production. Nazneen holds a Master's degree in Chemical Engineering from the University of Southern California, obtained between 1999 and 2001.
SVTC
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SVTC Technologies provides development and commercialization services for innovative semiconductor process-based technologies and products, cost-effectively and in an IP-secure manner. Through facilities in San Jose, California, and Austin, Texas, SVTC serves customers in rapidly growing markets such as novel memory, novel transistors, logic, MEMS, biotechnology, image sensors and photovoltaics. SVTC offers a suite of leading-edge equipment and services, including full-scale 8-inch and 12-inch process capabilities, advanced CMOS and non-CMOS equipment, analytical services, development support tools and commercialization services. SVTC is ISO 9001 certified and ITAR registered. SVTC's investors include Oak Hill Capital Partners, Tallwood Venture Capital and the company's management and employees. SVTC Technologies is an equal opportunity employer.