Ajay Patidar is a SRAM Design Engineer with six years of experience in memory design and high-speed data path. They began their career as an AMTS Engineer at DXCorr Design Inc from 2018 to 2019, followed by a role as a Senior Engineer at Sankalp Semiconductor from 2020 to 2022. Ajay continued as a Senior Engineer at Synopsys Inc from 2022 to 2023 and is currently serving as a Staff Engineer in R&D at Synopsys Inc. They hold a Master of Technology in Microelectronics and VLSI design from Shri G S Institute of Technology & Science and a Bachelor of Engineering in Electronics and Communication from the University Institute of Technology, RGPV.
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